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ASIC Design Engineer

Santa Clara, CA 
Area Code:
Travel Required:
Good understanding of computer architecture, logic design and VLSI design. 
Pay Rate:
Tax Term:
Date Posted:
Position ID:
Dice ID:

Job Description

Responsible for

  • Developing micro-architecture specifications for a next generation media processor. 
  • Designing and implementing video compression logic, image processing logic and processor cores in Verilog and SystemVerilog.
  • Synthesize and optimize RTL for timing, area and power.
  • Developing frontend methodologies and tool flows. 
  • Participating in chip bringup.

Requirements :

  • Master’s degree in Electrical Engineering with 0-5 years of experience. 
  • Good understanding of computer architecture, logic design and VLSI design. 
  • Knowledge of SystemVerilog, Verilog and Perl. 
  • Ability to program scripting languages, and the ablility to write assembly language programs. 
  • Strong communication skills and a good team player.


To apply, please submit resume with subject: JOB#120201.

Background check required if hired.

As an Equal Opportunity/Affirmative Action Employer, Ambarella recruits qualified applicants without regard to race, color, national origin, sex, physical disability, or veteran status.   


Ambarella Inc.
3101 Jay Street
Santa Clara, CA 95054