Responsible forDeveloping micro-architecture specifications for a next generation media processor.
Designing and implementing video compression logic, image processing logic and processor cores in Verilog and SystemVerilog.
Synthesize and optimize RTL for timing, area and power.
Developing frontend methodologies and tool flows.
Participating in chip bringup.
Master’s degree in Electrical Engineering with 0-5 years of experience.
Ambarella is an Equal Opportunity Employer.